Problem:

A manufacturer of biological microscopy products asked us to develop hardware, software and advanced FPGA components for the newest generation of a system that allows researchers to image and target specific cells of interest for investigating advanced cures for cancer and AIDS. This generation of an earlier device now must incorporate a PCIe interface, a multi-gigabit downstream link to the optics head and an optics head assembly with a high-resolution DMD. Also, it must be able to hold up to 1000 video frames in raw format, gray-scale format, and Huffman compressed formats and run these frames thru the exposure pipeline at greater than 3000 frames per second. There was also a design goal of incorporating a 32-bit microprocessor specialized toward microscopy operations.

Solution:

To meet these requirements, Bytes By Design developed the Windows application, firmware for a PC-side Xilinx Virtex-5 PCIe board and a custom optics head unit attached to the microscope also controlled by a Virtex-5. The custom head unit utilizes either a 1024x768 or 1920x1080 DMD controlled by the Virtex-5, 8MB frame memory, and a multi-gigabit data link. The multi-threaded Windows-based application that accepts and displays a digital video feed from the microscope and in turn allows the user to target cells by overlaying masks of a variety of user-drawn shapes or machine vision derived masks. The selected cells may then be photobleached by a variety of laser sources including a large-spot or optical galvo directed pinpoint source.

The Mosaic application gives the user control over various operating modes, selection of cells of interest, editing of image masks, loading of image memory buffers, a microcode assembler for the custom 32-bit microprocessor, and access to a variety of status, timing and control parameters.

The flip-view of the optics-head pc board shows the SFP multi-gigabit interface, the Virtex-5 gate array, RAM, the rear of the DMD (Digital Micromirror Device) and a variety of support logic. The design supports up to a 1920x1080 array of mirrors. The Virtex-5 implements the very substantial DMD interface and timing logic, multi-gigabit packet decode and assembly logic, SRAM image frame logic, a custom 32-bit microprocessor taylored to DMD image operations, and complex multi-port memory logic, FIFOs and multi-ported internal memories.